(Not Applicable)
1. Field of the Invention
The present invention is directed generally to memory circuits, and, more particularly, to a synchronous memory circuit with programmable read latency.
2. Description of the Background
Cache memories are used in computer systems to reduce the time required by a processor to access data that is stored in the main memory device of the computer system. Cache memories are usually placed between the processor and the main memory. Blocks of data (cache lines) from the slower main memory of the computer system are stored in duplicate in the higher-speed cache memory. A request for data is first presented to the cache memory. If the data is not stored in the cache memory, the request is presented to the main memory.
When a request for data is presented to a cache memory and the data is not stored in the cache, the failed access is termed a xe2x80x9ccache missxe2x80x9d. Because the access times of main memory devices are generally anywhere from four to twenty times longer than the access times of cache memories, it is important that the frequency of cache misses be minimized. One way to accomplish this goal is to increase the size of the cache memory used in the computer system. Increasing the size of the cache allows for the storage of more duplicative data in the cache. Thus, the number of cache misses will be reduced.
Increasing the size of a cache decreases the cache performance due to the effect of, inter alia, parasitic capacitance. The performance of a cache memory is measured in latency time. Latency is the time that it takes for data to appear on the external data bus after an address is presented to the cache.
Many modern devices typically have a cache memory in communication with a processor. Data in the cache memory is organized in blocks (also known as lines) usually comprising a plurality of external bus widths of data. For example, a cache line may comprise 256 bits and the external data bus comprises 64 bits. A group of four bus transactions is required to operate on one full cache line. This is referred to as a burst length of four, the burst length being the number of external data bus transactions that occur for each address presented to the cache when a full line operation occurs. The processor operates at a particular frequency that may not be compatible with the latency of the cache. Thus, data that is read out of the cache memory may not be present on the data bus at the desired time. Also, the width of the external data bus that connects the processor to the cache may vary from the internal data width of the cache. The difference in data widths between the data bus and the cache may cause the cache to have a different burst length of data accesses than the processor, although the external data bus burst length is common between the cache and the processor. Thus, if the internal data width of the cache is two times the data width of the external data bus, there is an internal burst length of two for the external burst length of four. The extra burst pair is manifested in data multiplexing to the external data bus at a rate which can be twice as great as the internal data transaction rate.
If the microprocessor requires a burst length of one, for example, only one of the two fetches is allowed to complete or both fetches complete but only the desired result is output to the external data bus. Thus, it is desirable to have a cache memory that has an internal latency time that can be adjusted to operate in conjunction with processors that require a different burst length. It is also desirable to have a cache memory that has an internal latency time that can be adjusted to operate in conjunction with processors that have varying operating frequencies.
The present invention, according to its broadest implementation, is directed to a logic circuit and a method for controlling the read latency time of a memory circuit. The logic circuit and method produce a plurality of values derived from a read enable signal. Each value represents the read enable signal delayed by a predetermined period of time. One of the values is selected in response to at least one control signal to enable a read operation of the memory circuit.
The present invention contemplates, in combination, an output stage of a memory circuit and a control logic circuit for controlling the read latency time of the memory circuit.
The present invention also contemplates a memory circuit which comprises a memory array, write control and addressing logic connected to the memory array, sense amplifiers connected to the memory array, output registers connected to the sense amplifiers, and read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of the output registers.
The present invention may also be part of a system, such as a cache memory system. The system may comprise a controlling device, a memory array, write control and addressing logic connected to the memory array, sense amplifiers connected to the memory array, output registers connected to the sense amplifiers, and read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of the output registers.
The present invention represents a substantial advance over prior methods and circuits for controlling the read operations of memory circuits. Because the present invention allows for programmable memory circuit read latency times, the present invention permits the efficient integration and operation of memory circuits connected to controlling devices with incompatible operational speeds. Those, and other advantages and benefits of the present invention, will become apparent from the Detailed Description of the Invention hereinbelow.